The present invention relates to a dynamic RAM (Random Access Memory) and a semiconductor device, and to a technology effective for application to a so-called open bit line type wherein dynamic memory cells are respectively placed at points where word lines and bit lines intersect.
According to investigations subsequent to the completion of the present invention, it has been revealed that Japanese Patent Application Laid-Open No. Sho 59(1984)-2365 (hereinafter called xe2x80x9cprior art 1xe2x80x9d), Japanese Patent Application Laid-Open No. Sho 60(1985)195795 (hereinafter called xe2x80x9cprior art 2xe2x80x9d), Japanese Patent Application Laid-Open No. Sho 60(1985)-211871 (hereinafter called xe2x80x9cprior art 3xe2x80x9d), and Japanese Patent Application Laid-Open No. Hei 9(1997)-135009 (hereinafter called xe2x80x9cprior art 4xe2x80x9d) have existed as those considered to be related to the present invention to be described later.
The prior arts 1 through 3 relate to a technology which makes use of even information storage capacitors using MOS capacity and supplies a voltage to each of plate electrodes employed in an open bit line type (one-intersection type or system). In the publication of the prior art 1, first wires crossed in a direction orthogonal to each bit line and connected at plural points, second wires for interconnecting the first wires with one another, and third wires for connecting central portions of the second wires to their corresponding power or source lines are provided to achieve the uniformity of accurate potential distributions of opposite electrodes of the information storage capacitors. In the publication of the prior art 2, a resistor is provided between two plate electrodes provided with a sense amplifier interposed therebetween to thereby delay a change in the potential of each plate electrode in association with a change in substrate voltage at the time that information stored in each memory cell is read out to a bit line. In the publication of the prior art 3, a plate electrode and wires for supplying voltages thereto are formed of a metal having a high melting point and low in resistance, or silicide of the metal and silicon. Alternatively, a plurality of metal wiring layers are provided on the plate electrode.
According to the prior art 1, a problem developed due to the fact that a source voltage changed according to the operation of a peripheral circuit is not transferred to the entirety of a plate electrode, is solved by laying out voltage-supplying power or source wires at plural points of the plate electrode and uniformizing the potential of the plate electrode on the whole according to the change in potential due to the operation of the peripheral circuit. According to the prior art 2, a problem developed due to the fact that a relative potential change differs from a change in potential on the substrate side, is solved by connecting the two plate electrodes through a resistor having a time constant associated with the change in potential on the substrate side. In the prior art 3 on the other hand, the problem that a change in potential supplied to each plate electrode from its corresponding bit line through a storage capacitor would lead to the application of a voltage to the plate electrode, is solved by reducing the resistance of each wire connected to the plate electrode.
It has been desirable to reduce the cost of a dynamic RAM (hereinafter called simply xe2x80x9cDRAMxe2x80x9d). To this end, a reduction in chip size is most effective. A scale-down has heretofore been pushed forward to reduce a memory cell size. It is however necessary to change even an operating mode or system of a memory array and thereby make a further reduction in cell size. By changing the operating mode of the memory array from a two-intersection type to a one-intersection type, the cell size can ideally be reduced to 75% by using the same design rule. However, the one-intersection type memory array has a problem in that array noise placed on each bit line or the like is high, as compared with the two-intersection type memory array. Thus, a product application becomes difficult unless it is solved.
Therefore, a discussion has been made of noise developed when the memory cells employed in the conventional two-intersection type are used as they are to configure the one-intersection type memory array. Thus, it has been revealed that an unneglible parasitic capacity has existed between each bit line and the plate electrode when the memory cell is a COB (Capacitor over Bit-line) cell, so-called deep hole STC (such cylinder shape that a lower electrode SN of each capacitor is formed on an inner wall of a hole defined in an interlayer dielectric) except for the MOS capacity. Even if the techniques described in the prior arts 1 to 3 are used as they are to perform the supply of a voltage, it has been found out that the array noise placed on the bit line, could not be reduced.
A description will be made of degradation in operating margin for each memory array due to plate noise by reference to FIGS. 16A and 16B. In the worst case of a one-intersection memory array shown in FIG. 16A, bit lines in a selected mat are all amplified to a low level (L) except for one bit line according to an amplifying operation of each sense amplifier, and bit lines in a non-selected mat are all amplified to a high level (H) except for one bit line. At this time, there is a danger that only one bit line in the selected mat, on which a high-level (H) signal appears, is subjected to noise from a plate electrode, whereby the signal would be amplified erroneously.
Now consider, as one example, where a word line WL0 is activated so that a high-level (H) signal appears on a bit line BL1T alone and a low-level (L) signal is read out onto other bit lines BL0T and BL2T and the like. Further, the high-level (H) signal developed on the bit line BL1T is regarded as small due to the reason such as the leakage or the like of an electrical charge for holding information in each memory cell. When a sense amplifier is activated, such bit lines BL0T/B, BL2T/B, etc. that signals greatly appear between complementary bit lines, are amplified fast in signal.
On the other hand, a bit line BL1T/B small in signal is slow in amplifying rate. At this time, negative noise is developed in a plate electrode PL0 of a selected mat from the bit lines BL0T, BL2T, etc. through a parasitic capacity CBLSN and a memory cell capacitor CS between storage nodes SN. To the contrary, positive noise is produced in a plate electrode PL1 of a mat adjacent thereto from bit lines BL0B and BL2B, etc. When these noise are returned from the plate electrode PL1 to the bit line BL1T/B on which a reverse signal appears, through the capacitor CS and the parasitic capacity CBLSN, a signal amount decreases so that the bit line is reversed erroneously.
Thus, the open bit line type memory array referred to above gets into great danger that information is erroneously read when the amount of a signal charge stored in each memory cell decreases. This leads to degradation in refresh characteristic and can result in a great reduction in yield of a DRAM. While the above description has been made with the noise developed in each plate electrode as an example, there is a fear of noise having a similar mechanism being produced even in a non-selected word line WL and a substrate for each memory cell. These noise degrade a read margin for the memory array.
An object of the present invention is to provide an open bit line type dynamic RAM and a semiconductor device capable of improving an operating margin. Another object of the present invention is to provide a dynamic RAM and a semiconductor device capable of achieving high integration and the stabilization of their operations. The above, and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in the present application will be described briefly as follows: In a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.